Verification with SystemVerilog

Course Outline

Verification with System Verilog is designed to help verification engineers use SystemVerilog for verification.  This course is also a very good entry point for new college graduates to start their careers in Verification.  The course has been designed to make it effortless to traverse through the course work.  Examples are presented at every step, and sufficient labs are provided to understand the concepts practically.

This course can be customized and paced based on the experience level of the engineers.


Basic understanding of Verification concepts, knowledge of Verilog as a Design or Verification Language.  Must have worked on some part of a design or verification project.

Course Syllabus

Introduction to SystemVerilog

  • Key features in System Verilog
  • Advantages of using System Verilog over Verilog for Verification
  • New Data Types in System Verilog 2 state and 4 state
  • User Defined Data types
  • Enumerated Data types
  • Structures and Unions
  • Wire Concatenation and Replication operators
  • Procedural Blocks
  • Tasks and Functions
  • Examples for using tasks and functions
  • Loops


  • Packed and Unpacked Arrays
  • Array Querying functions
  • Initializing of arrays
  • Dynamic Arrays
  • Built in methods and operators for dynamic arrays
  • Associative Arrays
  • Built in Methods and operators for Associative arrays
  • Queues
  • Queue operators and methods
  • Lots of examples


  • System Verilog layered test bench overview
  • Introduction to the interface layer for connecting between the DUT and the testbench
  • Connecting Interfaces and ports
  • Grouping signals using modports
  • Using clocking blocks in interfaces
  • Arbiter Lab using all the above concepts

Program Blocks

  • Program block details
  • Timing regions
  • Static Storage and Automatic Storage
  • Lab to create tetsbench program for arbiter test
  • OOP
  • Classes
  • Class object and handles
  • Class Property
  • Class Methods
  • Examples
  • Allocation and deallocation of memory for object
  • How to Copy objects
  • Virtual Methods
  • Extended classes
  • Casting
  • Virtual Classes
  • Lab for Creating a testbench using OOP


  • Constrained Random Verification
  • Random Variables and Methods Available in System Verilog
  • Inline Constraints and Global Constraints
  • Disabling Constraint blocks
  • Defining Constraints in a file
  • Static Constraints
  • Constraints in a Range
  • Implication
  • Solve before constraint
  • Weighted Random distribution
  • Lab examples

 InterProcess Communications

  • Semaphore classes
  • Mailbox classes
  • Events
  • Lab examples


  • Code Coverage
  • Functional Coverage
  • Coverage convergence
  • Creating Cover groups
  • Coverage bins
  • Conditional Coverage
  • Lab examples


  • SVA
  • Building block for assertions
  • Immediate Assertions
  • Concurrent Assertions
  • Examples for Assertions