ASIC Design and Verification

This is a good course to understand how a concept is taken through the Design and Verification cycles.  The course teaches fundamental Design concepts and emphasizes on SystemVerilog based Verification.  This is a necessary first step for the Advanced Verification course.

1. Fundamentals of logic design, Combinatorial , sequential , State machine design Verilog concepts for combinatorial, sequential and state machine design Understanding blocking and non blocking statements.
2. Memory basics and timing . FIFO design. Create a simple lab to build a FIFO in verilog and compile it.
3. Test bench overview. Defining tasks and functions in the test bench. Define state machines.  Clock generator overview. Build a self testing test bench for the FIFO you just designed.
4. SystemVerilog Introduction . Go over the constructs used in SystemVerilog.
5. Interfaces. How to use interfaces in SystemVerilog. Creating a SystemVerilog test bench for the verilog FIFO DUT.
6. Introduction to object oriented programming . Understanding of classes, objects, object members, object methods, Constructors ,static class members , static class methods, Inheritance and subclasses, understanding super keyword, virtual classes . Modify the test bench for the FIFO to use classes.
7. Randomization. Learn Constrained Random verification. Modify the FIFO test bench to use constrained random verification.
8. Coverage. Functional Coverage and assertions. Add Coverage to the FIFO
9. Introduction to Verification Methodologies which is a very good introduction for the advanced verification course.

Additional Important Information

• Lectures go in pace with the Lab work.
• We Use Cadence tools for all our ASIC training services.

Fees

• Please submit a Contact Request form for more information.

 

 

 

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