Sr. Verification Engineer

10 or more years of experience with various verification flows, with a proven track record of delivering successful ASICs in production.

  • Should be experienced in Architecting a verification environment for multi million gate ASICs.
  • Candidate should have worked on at least two full chip Verifications involving Test Plan, Development and Execution.
  • Experience with object oriented verification languages SystemVerilog and C++ is a must.
  • Expertise in one or more Verification Methodologies like OVM/VMM/UVM.  UVM Preferred
  • Experience with Assertions and Coverage
  • Should have knowledge of Networking or SoC Protocols like 802.3, 802.11, PCIe, DDR2/3, AMBA AHB/AXI
  • Should be a power user of scripting languages like Perl/Tcl.

MSEE Preferred

Apply by sending your resume to [email protected].