Krispan has some of the best talent pool of ASIC/FPGA Verification engineers. Our team has the best of both worlds, the depth of our very experienced engineers and the mindset that ‘We can do it’. Our engineers can help with:
- Define and document verification architecture
- Provide recommendations on verication methodologies, reusability and schedule risks
- Create automated test benches using different verification methodologies based on requirements
- Expertise in SystemVerilog, UVM, OVM, VMM, Vera, Verilog and Constrained Random Testing
- Migrating an existing testbench into a UVM based test bench.
- Integrating Verification IPs from different vendors.
- Developing Verification IPs
- Provide Functional, and ~100% code coverage!
- Create a list of all the functions and check which of those are exercised by functional coverage. Extract a metric for an executable verification plan
- Create Regression suites.
- Provide software methodologies to verify hardware.
- Amazing Register scripts, for generating Verification and Software Headers and classes. These scripts generate RTL for standard Bus interfaces for different type of registers. Also, generate XML for use in documentation.
Please submit a Contact Request form for more information.